CY7C1041CV334-Mbit (256K x 16) Static RAMFunctional Description[1]Features Pin equivalent to CY7C1041BV33The CY7C1041CV33 is a high-performance CMOS StaticRAM organized as 262,144 words by 16 bits. Temperature RangesWriting to the device is accomplished by taking Chip Enable(CE) and Write Enable (WE) inputs LOW. If Byte LOW Enable(BLE) is LOW, then data from I/O pins (I/O0–I/O7), is writteninto the location specified on the address pins (A0–A17). If ByteHIGH Enable (BHE) is LOW, then data from I/O pins(I/O8–I/O15) is written into the location specified on theaddress pins (A0–A17).— Commercial: 0 C to 70 C— Industrial: –40 C to 85 C— Automotive-A: –40 C to 85 C— Automotive-E: –40 C to 125 C High speed— tAA 10 ns Low active powerReading from the device is accomplished by taking ChipEnable (CE) and Output Enable (OE) LOW while forcing theWrite Enable (WE) HIGH. If Byte LOW Enable (BLE) is LOW,then data from the memory location specified by the addresspins will appear on I/O0 – I/O7. If Byte HIGH Enable (BHE) isLOW, then data from memory will appear on I/O8 to I/O15. Seethe truth table at the back of this data sheet for a completedescription of Read and Write modes.— 324 mW (max.) 2.0V data retention Automatic power-down when deselected TTL-compatible inputs and outputs Easy memory expansion with CE and OE features Available in Pb-free and non Pb-free 44-pin 400-milSOJ, 44-pin TSOP II and 48-ball FBGA packagesThe input/output pins (I/O0–I/O15) are placed in ahigh-impedance state when the device is deselected (CEHIGH), the outputs are disabled (OE HIGH), the BHE and BLEare disabled (BHE, BLE HIGH), or during a Write operation(CE LOW, and WE LOW).The CY7C1041CV33 is available in a standard 44-pin400-mil-wide body width SOJ and 44-pin TSOP II packagewith center power and ground (revolutionary) pinout, as wellas a 48-ball fine-pitch ball grid array (FBGA) package.Logic Block DiagramPin ConfigurationSOJ/TSOP IITop View256K 16ARRAYSENSE AMPSA0A1A2A3A4A5A6A7A8ROW DECODERINPUT BUFFERI/O0–I/O7I/O8–I/O15A9A10A 11A 12A 12A11A10Notes:1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at Semiconductor CorporationDocument #: 38-05134 Rev. *HDownloaded from 198 Champion Court San Jose, CA 95134-1709 408-943-2600Revised September 1, 2006

CY7C1041CV33Selection Guide-10Maximum Access TimeMaximum Operating ximum CMOS Standby 1090mA10mAmAAutomotive-E15mAPin Configurations48-ball FBGA(Top View)Document #: 38-05134 Rev. *HDownloaded from O1I/O 2A5A6I/O10 0A11NCHPage 2 of 12

CY7C1041CV33Pin DefinitionsPin Name44-SOJ,44-TSOPPin Number48-ball FBGAPin NumberI/O TypeDescriptionInputAddress Inputs used to select one of the addresslocations.A0–A171–5, 18–27,42–44A3, A4, A5, B3,B4, C3, C4, D4,H2, H3, H4, H5,G3, G4, F3, F4,E4, D3I/O0–I/O157–10,13–16,29–32, 35–38B1, C1, C2, D2,E2, F2, F1, G1,B6, C6, C5, D5,E5, F5, F6, G6Input/Output Bidirectional Data I/O lines. Used as input or output linesdepending on operationNC28A6, E3, G2, H1,H6No ConnectWE17G5Input/Control Write Enable Input, active LOW. When selected LOW, aWRITE is conducted. When selected HIGH, a READ isconducted.CE6B5Input/Control Chip Enable Input, active LOW. When LOW, selects the chip.When HIGH, deselects the chip.BHE, BLE40, 39B2, A1Input/Control Byte Write Select Inputs, active LOW. BHE controlsI/O15–I/O8, BLE controls I/O7–I/O0OE41A2Input/Control Output Enable, active LOW. Controls the direction of the I/Opins. When LOW, the I/O pins are allowed to behave asoutputs. When deasserted HIGH, I/O pins are tri-stated, andact as input data pins.VSS12, 34D1, E6VCC11, 33D6, E1Document #: 38-05134 Rev. *HDownloaded from Connects. This pin is not connected to the dieGround for the device. Should be connected to ground of thesystem.Power Supply Power Supply inputs to the device.Page 3 of 12

CY7C1041CV33Maximum RatingsStatic Discharge Voltage. . 2001V(per MIL-STD-883, Method 3015)(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature . –65 C to 150 CLatch-up Current. 200 mAAmbient Temperature withPower Applied. –55 C to 125 COperating RangeRangeAmbientTemperatureVCCCommercial0 C to 70 C3.3V 0.3VSupply Voltage on VCC to Relative GND[2] . –0.5V to 4.6VDC Voltage Applied to Outputsin High-Z State[2] .–0.5V to VCC 0.5VDC Input Voltage[2] .–0.5V to VCC 0.5VCurrent into Outputs (LOW) .20 mAIndustrial–40 C to 85 CAutomotive-A–40 C to 85 CAutomotive-E–40 C to 125 CDC Electrical Characteristics Over the Operating Range-10ParameterDescriptionTest ConditionsVOHOutput HIGH Voltage VCC Min., IOH –4.0 mA-12Min. Max.2.4Min.-15Max.2.40.4Min.-20Max.2.4Min.Max. Unit2.40.40.4VVOLOutput LOW Voltage VCC Min., IOL 8.0 mA0.4VVIHInput HIGH Voltage2.0VCC 0.32.0VCC 0.32.0VCC 0.32.0VCC 0.3VVIL[2]Input LOW ut LeakageCurrentGND VI VCCCom’l/Ind’l–1 1–1 1–1 1–1 1µAAuto-A–1 1–1 1µA–20 20µAOutput LeakageCurrentGND VOUT VCC, Com’l/Ind’lOutput DisabledAuto-A–1 1–1 1µA–1 1–1 1µA–20 20µAAuto-EIOZ–1 1–1 1Auto-EVCC OperatingSupply CurrentICCVCC Max.,f fMAX 5mA90mA40mA40mA45mA10mAAuto-EISB1ISB2Max. VCC,Automatic CECom’l/Ind’lPower-down Current CE VIHAuto-A—TTL InputsVIN VIH orVIN VIL, f fMAX Auto-E40Max. VCC,Automatic CECom’l/Ind’lPower-down Current CE VCC – 0.3V,Auto-A—CMOS InputsVIN VCC – 0.3V,or VIN 0.3V, f 0 rDescriptionCINInput CapacitanceCOUTI/O CapacitanceTest ConditionsMax.UnitTA 25 C, f 1 MHz, VCC 3.3V8pF8pFNotes:2. VIL (min.) –2.0V and VIH(max) VCC 0.5V for pulse durations of less than 20 ns.3. Tested initially and after any design or process changes that may affect these parameters.Document #: 38-05134 Rev. *HDownloaded from 4 of 12

CY7C1041CV33Thermal Resistance[3]ParameterΘJAΘJCDescriptionTest ConditionsThermal Resistance (Junction to Ambient) Test conditions follow standardThermal Resistance (Junction to Case) test methods and procedures formeasuring thermal impedance,per EIA / JESD51.TSOP-IIFBGASOJUnit42.9638.1525.99 C/W10.759.1518.8 C/WAC Test Loads and Waveforms[4]10-ns Devices12-, 15-, 20-ns DevicesZ 50Ω50 Ω* CAPACITIVE LOAD CONSISTSOF ALL COMPONENTS OF THETEST ENVIRONMENTR 317Ω3.3VOUTPUTOUTPUT30 pF*R2351Ω30 pF1.5V(b)(a)High-Z CharacteristicsR 317ΩALL INPUT PULSES3.0V90%90%OUTPUT10%10%GND3.3VR2351Ω5 pF(c)Rise Time: 1 V/ns(d)Fall Time: 1 V/nsAC Switching Characteristics[5] Over the Operating Min.-20Max.Min.Max.UnitRead Cycletpower[6]VCC(typical) to the first access100100100100µstRCRead Cycle Time10121520nstAAAddress to Data ValidtOHAData Hold from Address ChangetACECE LOW to Data ValidtDOEOE LOW to Data ValidtLZOEOE LOW to Low-ZtHZOEOE HIGH to High-Z[7, s8nstLZCECE LOW totHZCECE HIGH to High-Z[7, 8]tPUCE LOW to Power-UptPDCE HIGH to Power-Down10121520nstDBEByte Enable to Data Valid5678nstLZBEByte Enable to Low-ZtHZBEByte Disable to High-Z3350360000637006ns8ns07nsns8nsNotes:4. AC characteristics (except High-Z) for 10-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin loadshown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured 500 mV from steady-state voltage8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.9. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition ofeither of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates theWrite.Document #: 38-05134 Rev. *HDownloaded from 5 of 12

CY7C1041CV33AC Switching Characteristics[5] Over the Operating Range (continued)-10ParameterWrite in.Max.Unit[9, 10]tWCWrite Cycle Time10121520nstSCECE LOW to Write End781010nstAWAddress Set-Up to Write End781010nstHAAddress Hold from Write End0000nstSAAddress Set-Up to Write Start0000nstPWEWE Pulse Width781010nstSDData Set-Up to Write End5678nstHDData Hold from Write End0000nstLZWEWE HIGH to Low-Z[7]3333ns[7, 8]tHZWEWE LOW to High-ZtBWByte Enable to End of Write5768710810nsnsSwitching WaveformsRead Cycle No. 1[11, 12]tRCADDRESStAAtOHADATA OUTPREVIOUS DATA VALIDDATA VALIDRead Cycle No. 2 (OE Controlled)[12, 13]ADDRESStRCCEtACEOEtHZOEtDOEBHE, BLEtLZOEtHZCEtDBEtLZBEDATA OUTHIGH IMPEDANCEtHZBEDATA CCCC50%IISBSBNotes:10. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.11. Device is continuously selected. OE, CE, BHE and/or BHE VIL.12. WE is HIGH for Read cycle.13. Address valid prior to or coincident with CE transition LOW.Document #: 38-05134 Rev. *HDownloaded from 6 of 12

CY7C1041CV33Switching Waveforms (continued)Write Cycle No. 1 (CE Controlled)[14, 15]tWCADDRESSCEtSAtSCEtAWtHAtPWEWEtBWBHE, BLEtSDtHDDATA I/OWrite Cycle No. 2 (BLE or BHE Controlled)tWCADDRESSBHE, BLEtSAtBWtAWtHAtPWEWEtSCECEtSDtHDDATA I/ONotes:14. Data I/O is high-impedance if OE or BHE and/or BLE VIH.15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.Document #: 38-05134 Rev. *HDownloaded from 7 of 12

CY7C1041CV33Switching Waveforms (continued)Write Cycle No. 2 (WE Controlled, OE LOW)tWCADDRESStSCECEtAWtHAtSAtPWEWEtBWBHE, BLEtHZWEtSDtHDDATA I/OtLZWETruth y (ISB)LLHLLData OutData OutRead All BitsActive (ICC)LLHLHData OutHigh-ZRead Lower Bits OnlyActive (ICC)LLHHLHigh-ZData OutRead Upper Bits OnlyActive (ICC)LXLLLData InData InWrite All BitsActive (ICC)LXLLHData InHigh-ZWrite Lower Bits OnlyActive (ICC)LXLHLHigh-ZData InWrite Upper Bits OnlyActive (ICC)LHHXXHigh-ZHigh-ZSelected, Outputs DisabledActive (ICC)Document #: 38-05134 Rev. *HDownloaded from–I/O7I/O8–I/O15ModePowerPage 8 of 12

CY7C1041CV33Ordering InformationSpeed(ns)10Ordering 510651-8508744-pin TSOP II (Pb-Free)51-8510648-ball Fine Pitch BGA (Pb-Free)CY7C1041CV33-12VC51-8508244-lead (400-mil) Molded SOJCY7C1041CV33-12ZC51-8508744-pin TSOP II (Pb-Free)51-8508244-lead (400-mil) Molded SOJ (Pb-Free)CY7C1041CV33-12ZI51-8508744-pin TSOP II51-8508244-lead (400-mil) Molded SOJCY7C1041CV33-12ZXI44-pin TSOP II51-8508244-lead (400-mil) Molded SOJ51-8508744-pin TSOP II51-8508744-pin TSOP II44-pin TSOP II (Pb-Free)CY7C1041CV33-15VXIIndustrial44-lead (400-mil) Molded SOJ cial44-lead (400-mil) Molded SOJ ZIIndustrial44-pin TSOP II cial44-pin TSOP 4-lead (400-mil) Molded SOJ rial44-pin TSOP IICY7C1041CV33-10BAXACY7C1041CV33-12VXC2048-ball Fine Pitch BGA44-pin TSOP II (Pb-Free)CY7C1041CV33-10ZSXA1544-pin TSOP II48-ball Fine Pitch BGA (Pb-Free)CY7C1041CV33-10ZXI1244-lead (400-mil) Molded SOJ44-pin TSOP II rcial44-lead (400-mil) Molded SOJ ll Fine Pitch BGAOperatingRange48-ball Fine Pitch BGA e Type44-pin TSOP II (Pb-Free)CommercialCY7C1041CV33-20ZXC44-pin TSOP II (Pb-Free)CY7C1041CV33-20ZSXA44-pin TSOP II (Pb-Free)Automotive-A44-lead (400-mil) Molded d (400-mil) Molded SOJ (Pb-Free)51-8508744-pin TSOP II44-pin TSOP II (Pb-Free)Please contact your local Cypress sales representative for availability of these partsDocument #: 38-05134 Rev. *HDownloaded from 9 of 12

CY7C1041CV33Package Diagrams48-Ball (7.00 mm x 8.5 mm x 1.2 mm) FBGA (51-85106)BOTTOM VIEWTOP VIEWA1 CORNERØ0.05 M CØ0.25 M C A BA1 CORNERØ0.30 0.05(48X)12345664321CCFGDE2.6258.50 0.10E0.75AB5.25ABD8.50 0.105FGHH1.875AAB0.757.00 0.103.757.00 0.100.15(4X)0.15 C0.21 0.050.53 0.050.25 CB51-85106-*EDocument #: 38-05134 Rev. *HDownloaded from MAX.0.36SEATING PLANECPage 10 of 12

CY7C1041CV33Package Diagrams (continued)44-lead (400-mil) Molded SOJ (51-85082)51-85082-*B44-pin TSOP II (51-85087)51-85087-*AAll products and company names mentioned in this document may be the trademarks of their respective holders.Document #: 38-05134 Rev. *HPage 11 of 12 Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to beused for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize itsproducts for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypressproducts in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.Downloaded from

CY7C1041CV33Document History PageDocument Title: CY7C1041CV33 4-Mbit (256K x 16) Static RAMDocument Number: 38-05134REV.ECN NO.Issue DateOrig. ofChange**10951312/13/01HGKNew Data Sheet*A11244012/20/01BSSUpdated 51-85106 from revision *A to *C*B11285903/25/02DFPAdded CY7C1042CV33 in BGA packageRemoved 1042 BGA option pin ACC Final Data Sheet*C11647709/16/02CEAAdd applications foot note to data sheetDescription of Change*D11979710/21/02DFPAdded 20-ns speed bin*E262949See ECNRKF1) Added Lead (Pb)-Free parts in the Ordering info (Page #9)2) Added Automotive Specs to Datasheet*F361795See ECNSYTAdded Pb-Free offerings in the Ordering Information*G435387See ECNNXRRemoved -8 Speed bin from Product offering.Corrected typo in description for BHE/BLE in pin definitions table on Page# 3corrected ther Pin name from OE2 to OE.Included the Maximum Ratings for Static Discharge Voltage and Latch upCurrent.Changed the description of IIX current from Input Load Current toInput Leakage CurrentAdded note# 4 on page# 4Updated the Ordering Information table*H499153See ECNNXRAdded Automotive-A Operating RangeChanged tpower value from 1 µs to 100 µsUpdated Ordering Information tableDocument #: 38-05134 Rev. *HDownloaded from 12 of 12

4-Mbit (256K x 16) Static RAM CY7C1041CV33 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 . available on t he internet at 14 15 Logic Block Diagram Pin Configuration A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 COLUMN DECODER ROW DECODER SENSE AMPS INPUT BUFFER 25