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EE201: Digital Circuits and SystemsEE201:5 Digital Circuitrypage 1 of 31Digital Circuits and SystemsSection 5 – Digital Circuitry5.1 Classes- Bipolar Junction Transistors(BJTs)o TTL, LTTL, STTL, LSTTLo ECL, I(ntegrated)I(njection)L, D(Diode)TL- Metal Oxide Semiconductor (MOS)o PMOS, NMOS, CMOS5.2 Operational Parameters5.2.1 Voltage & CurrentVxy Voltage x defined as either Input or Output Voltage y defines either logic high or lowIxy Current x defined as either Input or Output Current y defines either logic high or lowVIHVILVOHVOL Min voltage at input which can be ‘read’ as a 1(high) Max voltage at input which can be ‘read’ as a 0(low) Min voltage at output which allows a 1(high) Max voltage at output which can be ‘read’ as a 0(low)IIH Input current when input 1IIL Input current when input 0IOH Output current when output 1IOL Output current when output 0

EE201: Digital Circuits and Systems5 Digital Circuitrypage 2 of 315VLogic 1VIHVILLogic 00V5.2.2 Fan-outo Max amount of inputs driven by output.ExampleDetermine the Fan-out of an NAND only circuit given the followingvalues:IOH 400 uA, IIH 60 uA, IOL 16 mA, IIL 1.6 mADuring high condition Each NAND gate provides 400 uA current at outputEach NAND gate sources 60 uA current at input.

EE201: Digital Circuits and Systems5 Digital Circuitrypage 3 of 31Fan-outHIGH IOH / IIH 400 / 60 6(Rounded down since cannot drive part of a gate!)During low condition Each NAND gate provides 16 mA current at outputEach NAND gate sources 1.6 mA current at input.Fan-outLOW IOL / IIL 16 / 1.6 10Fan-out of NAND gate is the lower value Fan-out 65.2.3 Propagation Delayso Delay when switching from one logic level to anothero tPHL Falling delay, delay incurred when output changes fromHigh to Low.o tPLH Rising delay, delay incurred when output changes fromLow to High.

EE201: Digital Circuits and Systems5 Digital Circuitrypage 4 of 315.2.4 Power Requirementso Usually the supply current ICC is given Power Vcc * Icco ORICCH and ICCL are given.ICCH : ICC when all outputs HIGHICCL : ICC when all outputs LOWo Power determined by speedo Charging and Discharging of Capacitances, etc.5.2.5 Noise Immunityo Circuit must be able to tolerate some noise at input withouterroro Calculate Noise Immunity of CircuitooDetermine ‘how much’ Input Noise voltage can be tolerated withoutchange in output stateMust be determined for both positive and negative noise5VLogic 1Logic 1VOHVNHVIHVILVNLVOLLogic 0Logic 0OUTPUT VoltageINPUT Voltage0V

EE201: Digital Circuits and Systems5 Digital Circuitrypage 5 of 31 When output is HIGH, Noise voltages more Negative than VNLwill push output into undetermined valueo VNL VIL - VOL When output is LOW, Noise voltages more Positive than VNH willpush output into undetermined value5.3 Transistor Transistor Logic (TTL) Uses Bipolar Junction Transistors (BJT) & Resistors to formlogic function Transistors used to perform logic and signal modification5.3.1 TTL Configurations Standard TTL Logic 0 : 0V-0.8V VIL Logic 1 : 2V-5V VIH Switching speed : 10nS Power Consumption : 10mW High Speed Improved (HS)-TTL Transistor (6nS : 22mW) Schottky TTL (3nS : 22mW) Low Power Low Power TTL Improved (LP)- Schottky Low Voltage (LV)-TTL (VDD 3.3V)5.3.2 TTL Outputs Totem-Pole Output Open Collector Output Tri-State Output

EE201: Digital Circuits and Systems5 Digital Circuitrypage 6 of 315.3.3 Standard TTL5.3.3.1 74XX TTL InverterA01Q1ONOFFQ2 Q3OFF OFFON ONF10When A is high ( 2V) Q1 has reverse biased base emitter Current Flows through base of Q1 into base of Q2 (Q2B) Q2 is ON, pulling F to GND.When A is low ( 0.8V) Q1 has forward biased base emitter Current charge in Q2B is discharged through A, turning Q2OFF. IL -1.6mA F pulled high (5 minus voltage drop across resistor)Properties Open Collector Output: Output F ‘floats’ high when input is 0. Can only Sink current at output. Open Collector output requires a pull up resistor on output toensure proper logic levels.Open Collector Resistor Try to minimise resistor value to ensure maximum switchingspeed. Minimise voltage swing between 0 and 1

EE201: Digital Circuits and Systems5 Digital Circuitrypage 7 of 31Resistor value:R ( 5 - VOUT)/IOUT VOUT depends on TTL logic levels, must be 2.0V plus somemargin of error. IOUT depends on how many inputs driven by output. IOUT must be greater than n*IIH where IIH in the high inputcurrent and n is the number of outputs.ExampleDesign open collector inverter which must provide TTL logic levels 100 % tolerance. The output is to drive 3 TTL inputs which have ahigh input current requirement of 60uA, IIH 60 uA.VOUT 2V 2V 4VIOUT 180uA, Round to 200uA.R (5 – 4)/ 200uA 5.3.3.2 TTL NAND5KΩ (Max Resistor Size)

EE201: Digital Circuits and Systems5 Digital Circuitrypage 8 of 31When A and B are high ( 2V) Q1 is reverse biased base emitter Current flows through base of Q1 into base of Q2 (Q2B) Q2 is ON, pulling Q3B to GND so Q3 is OFF. Q4 in ON, pulling F to GND (0.4V)When either A or B is low ( 0.8V) Q1 is forward biased base-emitter. Q1 is ON, discharging current in Q2B, switching Q2 OFF. Q3 is saturated, Pulling F to 5V (minus Voltage drop acrossresistor & VCE of Q3 : 3.1V) Q4 is OFFTTL NAND Truth Q4OFFOFFOFFONProperties Circuit Uses Totem Pole Output. Q3 and Q4 provide totem pole outputs. Q3 pulls up and Q4 pulls down. Faster than Pull-up Resistor. Can Sink and Source current. TTL NOR gate follows similar principlesF1110

EE201: Digital Circuits and Systems5 Digital Circuitrypage 9 of 315.3.4 TTL Loading Rules Needed to determine the Fan-out of a TTL circuit. Defines input/output loading conditions in terms of currento Unit loads (U.L) 40uA in HIGH state 1.6mA in LOW stateo Example : TTL Input Rated at 1 U.L Will draw(sink) 40uA when HIGH Will source 1.6mA back when LOW5.3.4.1 Current Sinking Q1 OFF, Q2 ONQ2 acting as sink for other TTL inputsRQ2 non-zero Voltage drop VOL producedTTL limits VOL(MAX) to 0.4Vo IOL is limited by VOLo Fan-out is limitedIOL is limited because VOL must be 0.4V

EE201: Digital Circuits and Systems5 Digital Circuitrypage 10 of 315.3.4.1 Current Sourcing Q1 ON, Q2 OFF Q1 acting as source for other TTL inputs If n*IIH is too high, IOH will be too high.o Higher IOH Larger drop across R (right of R1),Q1 and Do Lower VOH TTL limits VOH(MIN) to 2.4Vo IOH is limited by VOHo Fan-out is limited

EE201: Digital Circuits and Systems5 Digital Circuitrypage 11 of 315.3.5 Data Busing Data Bus forms common path between inputs & outputs ofmultiple logic circuits Allows data to be transferred between logic circuits Methods of Data Busing1) Wired-AND (using Open-Collector)2) Tri-State Logic (usually using totem-pole)5.3.5.1 Wired-AND Connect Open-Collector outputs to shared bus If A or B 0, Data bus is 0 If A B 1, Data bus value is 1 Bus line performs AND function Resistors not needed at every O/P Minimise for speed but maximise to limit IOLMAX If A 0, B 1. R must be large enough to ensuresink current is IOLMAX To Transfer data Ensure output B is 1 Bus Line will track changes in logic value of A

EE201: Digital Circuits and Systems5 Digital Circuitrypage 12 of 311. When A 0, Bus Line 02. When A 1, Bus Line 1ExampleSequence, S 0,1,1,0 sent from A along bus:B, C, D must be tied high.A Sends 0, Bus Line 0A Sends 1, Bus Line 1A Sends 1, Bus Line 1Etc Totem Pole output cannot be wired-ANDed Rc output resistor is too small Each output would have to sink too much current130Ω130ΩSuppose: Output from A 1 and Output from B 0 Current Sourced from A and Sunk in BCurrent, I, determined by voltage drop across Q1 (top left), D and Q3(bottom right) Q1 and Q3 VCE(SAT) 0.2V, D 0.7VI (5 – 0.7 – 0.2 - 0.2) / 130 30mA

EE201: Digital Circuits and Systems5 Digital Circuitrypage 13 of 31TTL defines IOL(max) 16mA, so wired-ANDed TTL current would bemore than allowed.Problem is worse if more than 2 TTL circuits are connected5.3.5.2 Tri-state With open collector, bus switches between 0(LOW) and 1(FLOAT) Open collector performance limited by resistorHow to take advantage of totem pole in data-busing?Totem-pole has 2 logic levels : 0(LOW) and 1(HIGH)Additional state added, High impedanceHigh Impedance (Hi-Z)Connection looks like open-circuitHigh Input impedance blocks input currentTri-State TTL NAND gate

EE201: Digital Circuits and SystemsEn00001111A001100115 Digital FOFFOFFOFFONQ3OFFOFFOFFOFFONONONOFFEn10page 14 of 31Q4OFFOFFOFFOFFOFFOFFOFFONF 2.4V 2.4V 2.4V 2.4V5V5V5V0VF!(A.B)Hi - ZA1B1C1 1A2F A3.B3B2C2 1A3B3C3 0Only 1 Enable ( !C in Fig) line can be 1 at any timeHi-ZHi-ZHi-ZHi-Z1110

EE201: Digital Circuits and Systems5 Digital Circuitrypage 15 of 315.3.6 Schottky TTLSBD Uses low forward voltage drop to limit transistor saturationo SBD has forward voltage drop of 0.25Vo Collector-base forward bias by more than 0.25Vo Stops transistor from going deep into saturation allowingfaster switching off (less to discharge).o Switching speed further improved by smaller resistorsSchottky TTL Properties Propagation delay for single gate reduced to 3nS Power dissipation per gate is 23mWLow Power Schottky TTL Increase resistor value to reduce PD to 2mW Gate propagation delay increased to 9nS

EE201: Digital Circuits and Systems5 Digital Circuitrypage 16 of 315.4 Emitter Coupled Logic (ECL)The term ECL stands for Emitter Coupled logic, which is a bipolarcircuit technology. ECL has the fastest switching speed of any logicfamily, but its power consumption is much higherECL Logic Levels:Logic 1 -0.8VLogic 0 -1.7V5.4.1: Emitter Coupled Logic inverter/bufferVIN -1.7V (logic 0) Q1 is OFF but Q2 is ON. Q3 is OFF VOUT1 -0.8V (logic 1)Ö VC1 0Ö VC2 -0.9 Q4 is ON VOUT2 -1.7V (logic 0)VIN -0.8 (logic 1) Q1 is ON but Q2 is OFF.Ö VC1 -0.9 Q3 is ON VOUT1 -1.7V (logic 0)Ö VC2 0 Q4 is OFF VOUT2 -0.8V (logic 1)

EE201: Digital Circuits and Systems5 Digital Circuitrypage 17 of 31Q1 and Q2 cannot be on at the same time.Neither operates in saturation.Ö Faster SwitchingCircuit provides both Inversion (VOUT1) and buffering (VOUT2)Q3 and Q4 are emitter follower functions and produce ECL logic levels5.3: Emitter Coupled Logic OR/NORWhen either A or B -0.8V (logic 1) QA or Q1 is ON but Q2 is OFF. Q3 is ON VOUT1 -1.7V (0)Ö VC1 -0.9VÖ VC2 0V Q4 is OFF VOUT2 -0.8V (1)When A B -1.7 (logic 0) QA and Q1 are OFF but Q2 is ON. Q3 is OFF VOUT1 -0.8V (logic 1)Ö VC1 0Ö VC2 -0.9 Q4 is ON VOUT2 -1.7V (logic 0)A0011V OUT 1 A BB0101VOUT11000VOUT20111V OUT 2 A B

EE201: Digital Circuits and Systems5 Digital Circuitrypage 18 of 315.4: ECL PropertiesTypical Propagation delay time is 1nS Fan-out is typically about 25. Low Impedance emitter-followeroutputs5.4: ECL Advantages The transistors never saturate and so switching speed is veryhigh., which makes ECL a little faster than advanced SchottkyTTL An ECL logic block usually produces an output and itscomplement. This eliminates the need for inverters. The total current flow in an ECL circuit remains relativelyconstant regardless of its logic state.o Steady current requirement ensures no noise spikes duringtransitions. Output signals very clean5.4: ECL Disadvantages Low noise margins, approx 250mV. Difficult to use in noisyenvironments such as automobile, RF, etc. High power dissipation due to constant current flows.PD 25mWgate. Higher than 74 TTL series. Negative power supply need. Makes circuit very expensive ifinterfaced to non-ECL components such as TTL, CMOS

EE201: Digital Circuits and Systems5 Digital Circuitrypage 19 of 315.5 Integrated Injection Logic (I2L) A digital circuit composed of bipolar transistors. It hasrelatively fast switching speeds and utilizes little power Similar speed to TTL but less power VccRext VccIIOutQ1InOutQ2InQ20V0VQ1 (PNP) is always on. The current passing into base of Q2 dependson the resistor value, Rext.The input connection is either high-impedance floating (Logic 1) or isconnected to 0V as a current sink (Logic 0)When input is open (Hi-Z), current I flows into base of Q2, switchingQ2 ON and pulling the output to ground, Out 0.If the input is shorted to 0V (logic0), then I is shunted away from Q2’sbase, switching Q2 off to give a high impedance o/p(logic1).¾ Circuit is IIL inverter

EE201: Digital Circuits and Systems5 Digital Circuitrypage 20 of 31IIPAFQ3Q1IBQ2When both inputs are 0, P will be Hi-Z turning Q3 ON, F 0When either input is 1, P will be pulled to 0. Q3 will be off and F willbe Hi-Z 0VHi-ZHi-ZHi-Z0111F A BRemove Q3 to make an NOR operationProperties of IIL: No internal resistors needed : Larger integration possibleo 10 times the component density than TTL Speed & Power can be tailored for applicationo Low power application : Large Rext tp 100ns, PD 5nWo High Speed application : Small Rext tp 5ns, PD 5mW Can be used in wired-AND data bussing

EE201: Digital Circuits and Systems5 Digital Circuitrypage 21 of 315.6 MOS TechnologyMOSFET : Metal Oxide Semiconductor Field Effect TransistorFIX P-Channel .Source is at the topN-Channel MOSFET When VGS VTH (ie VGS 0), Reverse biased p-n junction between Sand D. No electron flow between source and drain. MOSFET isOFF. When VGS VTH, Electrons are attracted to gate creating n-typeconductive channel is formed under oxide. MOSFET is ON. PMOS is opposite. Requires negative VGS voltage to draw holes togate.

EE201: Digital Circuits and Systems5 Digital Circuitrypage 22 of 315.6.1 NMOS Logic Use only N-Channel MOSFETso When VGS VDD, Ron 1KΩo When VGS 0, Roff 1010ΩVin0VVDDMOSFETRoff 1010ΩRon 103ΩVoutVDD 0VNMOS NAND GateA0V0VVDDVDDB0VVDD0VVDDFVDDVDDVDD0V

EE201: Digital Circuits and Systems5 Digital Circuitrypage 23 of 31NMOS NOR GateA0V0V5V5VB0V5V0V5VF5V0V0V0VF A BNMOS Properties Speed : 50ns Power : 0.1mW/gate Noise Margin 1.5V when VDD 5V Fan Out 50NMOS Advantages: Simple Fabrication Processo Only Single Gate is Needed High Density :o Only loading “resistor” neededNMOS Disadvantages: Static Charge Build-Upo Need circuitry to protect against. Slow 0- 1 Change High Power Consumptiono When output is low, Current flows across NMOS gate Power consumed when idle.

EE201: Digital Circuits and Systems5 Digital Circuitrypage 24 of 315.7 CMOS Logic Utilises both NMOS and PMOS gates togethero Complementary and Symmetrical DesignVIN0VVDDQ1ON(103Ω)OFF(1010Ω) V OUT V INQ2OFF(1010Ω)ON(103Ω)VOUTVDD0V

EE201: Digital Circuits and Systems5 Digital Circuitry5.7.2 CMOS NOR GateWhen A 0V and B 0VÖ P0 and P1 are ON. N0 and N1 are OFF. F is pulled high to VDDWhen either A or B is VDDÖ Either N0 or N1 will be ON F is pulled low to GNDA0V0VVDDVDDF A BB0VVDD0VVDDFVDD0V0V0Vpage 25 of 31

EE201: Digital Circuits and Systems5 Digital Circuitrypage 26 of 315.7.3 CMOS NAND Gate N0 and N1 must be ON to connect F to GND.Ö A and B must be VDD F is pulled to GNDWhen either A or B is 0VÖ Either P0 or P1 is ON and either N0 or N1 blocks path toGND F is pulled to VDDA0V0VVDDVDDB0VVDD0VVDDF FVDDVDDVDD0V

EE201: Digital Circuits and SystemsY AB C5 Digital Circuitrypage 27 of 31

EE201: Digital Circuits and Systems5 Digital Circuitrypage 28 of 31CMOS PropertiesLoading Resistor not neededNoise Margin:VIL(max) 30% of VDDVIH(min) 70% of VDDVOH(min) VDD-0.05V, VOL(max) 0.05VNoise Margin 30% of VDDSpeed:Limited by circuit capacitanceInitially not as fast as TTL since input capacitance ishigher but can be minimised.Fan-out: MOSFET is voltage controlled device unlike BJT.Each transistor draws vary little current allowing large Fanout. However each additional gate input causes an increaseoutput capacitance and the delay of the circuit.CMOS PowerAlways one transistor ‘blocking’ path to groundIdeal CMOS would only dissipate when switching from high to low orhigh to low.Dynamic power consumption caused by changes in circuitcapacitances. Gate, Source, Drain and Wire capacitances must becharged and discharged during switching.Real CMOS also dissipates small amounts of power when idle Static Power due to leakageGate- source leakageSource- Drain leakageReverse Bias leakage

EE201: Digital Circuits and Systems5 Digital Circuitrypage 29 of 31At smaller technologies ( 130nm) the leakage is higher as insulationOxide is thinner Power Consumption Ratios for Altera FPGAAt 130nm : Dynamic 81%, Static 7%At 90nm : Dynamic 66%, Static 28%Short-Circuit Power: When switching logic level the input is floating,both transistors are on for a small period of time creating Path toground. Must account for floating inputs to prevent short circuit.Comparison of logic 02010221219101ECL GVGVGVGVG74C74HC74HCT74AC74ACT Fan-outPd(mW/gate)NoiseimmunityVGVGVGVGVGVGVGProp. delay 4.75355034512517550 606002106060100100Figures of merit can be calculated as product of propagation delay and power dissipationPdFor CMOS, Pd is static/dynamic(1MHz) and figure of merit is calculated for each.TotalPd staticPd DynamicPdVG VeryGood G Good P Poor

EE201: Digital Circuits and Systems5 Digital Circuitrypage 30 of 315.7 CMOS/TTL Interfacing: TTL driving CMOSWhen interfacing different types of IC’s, we must check that the driving device can meet the currentand voltage requirements of the load device. Examination of Table 1 indicates that the input currentvalues for CMOS are extremely low compared with the output current capabilities of any TTL series.Thus, TTL has no problem meeting the CMOS input current requirements.There is a problem, however, when we compare the TTL output voltages with the CMOS inputvoltage requirements. Table 2 shows that VOH (Min) of every TTL series is too low when comparedwith the VIH (Min) requirement of the 4000B, 74HC, and the 74AC series. For these situations,something must be done to raise the TTL output voltage to an acceptable level for CMOS.Table 1CMOSParameterIIH (max)IIL (max)IOH (max)IOL (max)4000B1 µA1 µA0.4mA0.4mA74HC/HCT1 µA1 µA4mA4mA74AC/ACT1 µA1 µA24mA24mA74AHC/AHCT1 µA1 µA8mA8mATTLParameterIIH (max)IIL (max)IOH (max)IOL (max)7440 µA1.6mA0.4mA16mA74LS20 µA0.4mA0.4mA8mA74AS20 µA0.5mA2mA20mA74ALS20 µA100 µA400mA8mA74F20 µA0.6mA1.0mA20mATable 2CMOSParameter 4000B 74HC 74HCT 74AC 74ACT 74AHC 74AHCT3.53.52.03.52.03.852.0VIH (min)1.51.00.81.50.81.650.8VIL (max)4.954.94.94.94.94.43.15VOH (min)0.10.10.10.10.440.1VOL (max) 10.7VNLTTLParameterVIH (min)VIL (max)VOH (min)VOL 0.374AS2.00.82.70.50.70.374ALS2.00.82.50.50.70.4

EE201: Digital Circuits and Systems5 Digital Circuitrypage 31 of 31The most common solution to this interface problem is shown in figure 1, where the TTL output isconnected to 5V with a pull-up resistor. The presence of the pull-up resistor causes the TTL outputto rise to approximately 5V in the High state, thereby providing an adequate CMOS input voltagelevel. This pull-up resistor is not required if the CMOS device is a 74HCT or a 74ACT because theseseries are designed to accept TTL outputs directly, as Table 2 shows.Figure 1 – External pull-up resistor is used when TTL drives CMOSCMOS Driving TTL in the HIGH StateTable 2 shows that CMOS outputs can easily supply enough voltage (VOH) to satisfy the TTL inputrequirement in the HIGH state (VIH). Table 1 shows that CMOS outputs can supply more than enoughcurrent (IOH) to meet the TTL input current requirements (IIH). Thus, no special consideration isneeded for the HIGH state.CMOS Driving TTL in the LOW StateTable 1 shows that TTL inputs have a relatively high input current in the LOW state, ranging from100µA to 2 mA. The 74HC and 74HCT series can sink up to 4 mA, and would have no troubledriving a single TTL load of any series. The 4000B series, however, is much more limited. Its low IOLcapability is not sufficient to drive even one input of the 74 or 74AS series. The 74AHC series hasoutput drive comparable to that of the 74LS series.

TTL defines I OL(max) 16mA, so wired-ANDed TTL current would be more than allowed. Problem is worse if more than 2 TTL circuits are connected 5.3.5.2 Tri-state With open collector, bus switches between 0(LOW) and 1 (FLOAT) Open collector performance limited by res